1. Field of the Invention
This invention relates to a light emitting diode chip, which has small package volume and which can be rapidly manufactured, and methods for manufacturing and packaging the light emitting diode chip.
2. Description of the Related Art
As shown in FIG. 1, a conventional light emitting diode chip 91 is electrically connected to external electrodes 93 on a substrate 92 by a wire bonding process. However, a larger space on the substrate 92 is required for the wire bonding process. In addition, since wire connections are made one by one using a machine during the wire bonding process, the production efficiency is relatively low and is unfavorable for a system in package or a wafer level package.
In order to alleviate the problems attributed to the wire bonding process, a flip chip process is commonly used for replacing the wire bonding process. However, in the flip chip process, there is a need to deposit plenty of gold bumps on each chip, which is time-consuming and also decreases the packaging process efficiency of the chip. Aside from the flip chip process, other packaging methods without using the wire bonding process are also proposed. For example, the chip can be flipped such that the electrodes on the chip are directly mounted onto the electrodes on the substrate without providing the gold bumps therebetween. However, in packaging method, those electrodes on the chip should be formed equally in height to have an excellent flatness. Therefore, the precision requirement for the electrodes is relatively high, and it is relatively difficult to manufacture the chips for such packaging method. Furthermore, another packaging method by modifying the structure of the chip has been proposed heretofore. According to this method, the electrodes of the chip extend from a top surface of the chip to a bottom surface thereof. For example, a method of making a chip disclosed in JP 2008-130875, as shown in FIGS. 2 and 3, includes: forming a via hole 941 in a chip 94, followed by forming a conductive layer 95 for electrically connecting an electrode 96 on a top surface of the chip 94 to an electrode 97 on a bottom surface of the chip 94. Therefore, the electrode 97 of the chip 94 can be provided on the bottom surface of the chip 94. However, in the case of JP 2008-130875, the via hole 941 defines a vertical via-hole sidewall. When forming the conductive layer 95 along the vertical via-hole sidewall, it is likely to result in a poor step coverage (non-uniform surface coverage) of the via-hole sidewall and a poor conductivity of the conductive layers.